Precharge voltage supplying circuit

ABSTRACT

A precharge voltage supplying circuit comprises a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The precharge voltage supplying circuit can be widely used in various devices which need the generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range of change of which is not so large.

BACKGROUND

The present disclosure relates to a semiconductor memory device and, more particularly, to a precharge voltage supplying circuit.

Recently, the capacity of semiconductor memory devices is rapidly becoming larger and studies on methods to increase an operational speed and reduce current consumption are steadily conducted. Particularly, techniques to reduce the current consumption are developed in a semiconductor memory device which can be embedded in a portable system such as a cellular phone or a notebook computer.

One of the above mentioned techniques is to minimize the current consumption in a core area of a memory. The core area having a plurality of memory cells, bit lines and word lines is designed according to a critical design rule. Thus, the memory cells can be very small and operate with a low power consumption.

Particularly, a bit line precharge technique is important to increase the speed of a cell data access. The bit line precharge technique precharges a bit line (BL) to a half level of a core voltage (VCORE) before the data access in order to increase the speed of the data access.

Meanwhile, in a standby state, a potential difference occurs between a word line (WL) of 0V and a precharged bit line (BL). If a bridge occurs between the word line (WL) and the bit line (BL), a current consumption increases due to the bridge current which is caused by the potential difference. Therefore, in order to reduce the current consumption caused by the bridge current, a precharge voltage supplying circuit, which has a bleeder resistance, is used to generate a precharge voltage (VBLP) on the bit line where a voltage drop occurs.

FIG. 1 is a block diagram of a conventional precharge voltage supplying circuit.

As shown in FIG. 1, the conventional precharge voltage supplying circuit includes a precharge voltage supplying unit 100 for outputting a precharge voltage VBLP in response to a clock enable signal CKE.

The precharge voltage supplying circuit outputs the precharge voltage VBLP in response to the clock enable signal CKE of a high level in a normal active state and of a low level in a power down mode.

However, in such a precharge voltage supplying circuit, the clock enable signal CKE can be either in a high level or in a low level at the time of a power-up. Thus, there is a problem that a DRAM wrongly operates since the precharge voltage VBLP is not normally supplied to the bit line and a corresponding bit bar line.

BRIEF SUMMARY

In an aspect of the present disclosure, a precharge voltage supplying circuit is provided comprising a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal, and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage. The first control signal is activated when the power-up signal is applied to the control signal generating unit. The control signal generating unit outputs the first control signal, which drives the bleeder circuit, in response to the clock enable signal after a predetermined time from an input of the power-up signal.

Another aspect of the present disclosure is directed to providing a precharge voltage supplying circuit comprising a precharge voltage supplying unit for supplying a precharge voltage in response to a power-up signal and a clock enable signal, and an equalization unit for precharging a bit line and a bit bar line by using the precharge voltage.

In another embodiment of the present disclosure, a precharge voltage supplying circuit is provided, comprising a control signal generating unit for generating a first control signal which is activated at the time of a power-up, a precharge voltage control unit for controlling a precharge voltage in response to the first control signal; and an equalization unit for precharging a bit line and a bit bar line by using the precharge voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional precharge voltage supplying circuit.

FIG. 2 is a block diagram of a precharge voltage supplying circuit according to an exemplary embodiment of the present disclosure.

FIG. 3 is a circuit diagram of a control signal generating unit in the precharge voltage supplying circuit of FIG. 2.

FIG. 4 is a circuit diagram of an example of a precharge voltage control unit in the precharge voltage supplying circuit of FIG. 2.

FIG. 5 is a circuit diagram illustrating another example of a precharge voltage control unit that can be used in the precharge voltage supplying circuit of FIG. 2.

FIGS. 6A and 6B are graphs illustrating a precharge voltage characteristic and a bridge current characteristic, respectively, in the circuit of FIG. 5.

FIG. 7 is a circuit diagram illustrating another example of a precharge voltage control unit that can be used in the precharge voltage supplying circuit of FIG. 2.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, the present invention will be described through examples and exemplary embodiments. The examples and exemplary embodiments merely exemplify application of the present invention, and the scope of the present disclosure and the appended claims is not limited by the examples and exemplary embodiments.

As shown in FIG. 2, a precharge voltage supplying circuit according to an exemplary embodiment of the present disclosure includes a precharge voltage generating unit 40 to produce a precharge voltage VBLP by using an internal voltage Vp in response to a power-up signal PWRUP, a clock enable signal CKE and a mode register set signal MRSP8, and an equalization unit 30 for precharging a bit line and a bit bar line by using the precharge voltage VBLP.

The precharge voltage generating unit 40 can include a control signal generating unit 10 for generating control signals BLEEDER_OFF and BLEEDER_OFFB (FIG. 3) in response to the power-up signal PWRUP, the clock enable signal CKE and the mode register set signal MRSP8 (FIG. 3) and a precharge voltage control unit 20 for controlling the precharge voltage VBLP in response to the control signals BLEEDER_OFF and BLEEDER_OFFB which are activated when the power-up signal PWRUP is applied to the control signal generating unit 10.

The mode register set signal MRSP8 is activated with the lapse of about 200 μs from the input of the power-up signal PWRUP.

As shown in FIG. 3, the control signal generating unit 10 includes a control unit 11 which is driven in response to the power-up signal PWRUP and the mode register set signal MRSP8, an operation unit 12 for performing a NAND operation of an output signal of the control unit 11 and an inverted signal of the clock enable signal CKE, and a signal generating unit 13 for outputting the control signals BLEEDER_OFF and BLEEDER_OFFB by buffering an output signal of the operation unit 12 in example of FIG. 3

The control unit 11 includes a pull-up driving unit P11 for pull-up driving node A in response to the power-up signal PWRUP, a pull-down driving unit N11 for pull-down driving node A in response to the mode register set signal MRSP8, and a latch unit 111 for latching a voltage signal at node A and for outputting the latched voltage signal to node B.

As shown in FIG. 4, in order to produce the precharge voltage VBLP, the precharge voltage control unit 20 includes a first bleeder circuit 21 which applies the internal voltage Vp as the precharge voltage VBLP to be supplied to the equalization unit 30, in response to the control signals BLEEDER_OFF and BLEEDER_OFFB, and a second bleeder circuit 22 which applies the internal voltage Vp as the precharge voltage VBLP to be supplied to the equalization unit 30, in response to a plurality of control signals BLEEDER_S, BLEEDER_M, BLEEDER_L and BLEEDER_XL which have different turn-on voltage levels.

The first bleeder circuit 21 includes a first driver N1 which applies the internal voltage Vp as the precharge voltage VBLP to be supplied to the equalization unit 30 in response to the control signal BLEEDER_OFF, and a second driver P1 which applies the internal voltage Vp as the precharge voltage VBLP to be supplied to the equalization unit 30 in response to the inverted signal BLEEDER_OFFB of the control signal BLEEDER_OFF.

The second bleeder circuit 22 includes third to sixth drivers N2, N3, N4 and N5 which apply the internal voltage Vp to the equalization unit 30 in response to the plurality of the control signals BLEEDER_S, BLEEDER_M, BLEEDER_L and BLEEDER_XL which have different turn-on voltage levels. As described above, the drivers P1 and N1 to N5 selectively supply the internal voltage Vp to the equalization unit 30 such that the precharge voltage VBLP has different voltage levels.

An example of operation of the precharge voltage supplying circuit of FIGS. 2-4 will be described by referring to the drawings.

The control unit 11 of the control signal generating unit 10 is driven in response to the power-up signal PWRUP and the mode register set signal MRSP8, and the operation unit 12 of the control signal generating unit 10 performs a NAND operation on the output signal of the control unit 11 and the inverted signal of the clock enable signal CKE.

The signal generating unit 13 buffers the output signal of the operation unit 12 to output the control signals BLEEDER_OFF and BLEEDER_OFFB.

That is, the control signal generating unit 10 pull-up or pull-down drives node A in response to the power-up signal PWRUP and the mode register set signal MRSP8. The control signal generating unit 10 activates the control signals BLEEDER_OFF and BLEEDER_OFFB regardless of whether the clock enable signal CKE is in a high level or in a low level by maintaining node B as a low signal through the pull-up driving unit P11 when the power-up signal PWRUP is applied to the control unit 11.

Then, since the first bleeder circuit 21 maintains a turn-on state in response to the control signals BLEEDER_OFF and BLEEDER_OFFB, the internal voltage Vp is supplied as the precharge voltage VBLP to the equalization unit 30.

That is, when the power-up signal PWRUP is applied to the control signal generating unit 10, the first driver N1 and the second driver P1 of the first bleeder circuit 21 are turned on regardless of the clock enable signal CKE, and the internal voltage Vp is supplied as the precharge voltage VBLP to the equalization unit 30 for the bit line precharge.

After a predetermined time, the mode register set signal MRSP8 is activated. Then, the pull-down driving unit N11 of the control signal generating unit 10 is driven so that node B is maintained as a high signal.

At this time, the control signals BLEEDER_OFF and BLEEDER_OFFB are activated in synchronization with the clock enable signal CKE, and the first driver N1 and the second driver P1 of the first bleeder circuit 21 are turned on in synchronization with the clock enable signal CKE.

Accordingly, in the precharge voltage supplying circuit of FIGS. 2-4, when the power-up signal PWRUP is applied to the control signal generating unit 10, the control signals BLEEDER_OFF and BLEEDER_OFFB are activated regardless of the clock enable signal CKE, and the first bleeder circuit 21 of the precharge voltage control unit 20 is driven to supply the precharge voltage VBLP to the equalization unit 30.

After a predetermined time from the input of the power-up signal PWRUP, the control signals BLEEDER_OFF and BLEEDER_OFFB are activated in synchronization with the clock enable signal CKE, and the precharge voltage VBLP is supplied to the equalization unit 30.

In the present invention, the bit line and the bit bar line are precharged to a precharge voltage level by the bleeder circuit with an input of the power-up signal, and a leakage current due to a word line bridge is also reduced.

FIG. 5 is a precharge voltage control unit according to another exemplar embodiment of the present disclosure. The precharge voltage control unit of FIG. 5 includes a first switch unit 31, a bleeder resistance unit 32 and a second switch unit 34 which connects node C to node D.

The first switch unit 31 includes a logic unit 300 and an NMOS transistor N30 which is connected between node C and node D and is turned on in response to an output signal of the logic unit 300. The logic unit 300 includes a NOR gate NR30 receiving a test mode signal TM_BLEEDER_PWDD and a ground voltage VSS to perform a NOR operation, and inverters IV30 and IV31. Here, it is desirable to design the NMOS transistor N30 to have a large size.

The bleeder resistance unit 32 includes an NMOS transistor N31 which is connected between node C to which the internal voltage Vp is supplied and node D to which the precharge voltage VBLP is supplied and operates in response to the control signal BLEEDER_S, and a resistance element R30 which is in parallel connected to the NMOS transistor N31 between node C and node D.

Operation of the precharge voltage control unit of FIG. 5 will be described below in detail.

The bleeder resistance unit 32 operates in accordance with the test mode signal TM_BLEEDER_PWDD. First, in a case that the test mode signal TM_BLEEDER_PWDD is in a low level, the output signal of the logic unit 300 is in a high level and the NMOS transistor N30 is turned on. Since the size of the NMOS transistor N30 is large, the voltage drop between node C and node D through the turn-on resistance of the NMOS transistor N30 is not so large. Thus, the precharge voltage VBLP, having a level which is almost the same as the internal voltage Vp, is output to the equalization unit 30 of FIG. 2 through node D. At this time, there is almost no voltage drop through the bleeder resistance unit 32 which includes the NMOS transistor N31 and the resistance element R30. Also, if the second switch unit 34 is turned on so that node C is connected to node D, operations of the NMOS transistor N31 and the bleeder resistance unit 32 are bypassed, and the precharge voltage VBLP, having a level which is almost the same as the internal voltage Vp, is output through node D.

Meanwhile, in a case that the test mode signal TM_BLEEDER_PWDD is in a high level, the output signal of the logic unit 300 is in a low level and the NMOS transistor N30 is turned off. Thus, a voltage drop of the internal voltage Vp occurs through the bleeder resistance unit 32 so that a voltage-dropped signal is output as the precharge voltage VBLP through node D. At this time, since the bleeder resistance unit 32 includes the NMOS transistor N31 and the resistance element R30, the second bit line precharge voltage VBLP is adjustable in various levels according to a PVT fluctuation and the range in the fluctuation is not so large. This is due to the characteristic of the NMOS transistor N31, which has various turn-on resistance values according to the PVT fluctuation, and the characteristic of the resistance element R30, which has a constant resistance value regardless of the PVT characteristic change.

Referring to FIG. 6A, although the precharge voltage VBLP, corresponding to a bridge resistance Rbr, has various levels according to the PVT fluctuation, the range in the fluctuation is not so large. As shown in FIG. 6B, the level of the precharge voltage VBLP is highest when the PVT fluctuation is “FFFH”, and the level of the precharge voltage VBLP is lowest when the PVT fluctuation is “SSSH”. Here, “FFFH” and “SSSH” show the PVT fluctuation. For example, “SSSH” means that a process speed of an NMOS transistor and a PMOS transistor is slow, a voltage is low, and a temperature is hot. Also, referring to FIG. 6B, although a bridge current Ibr has various levels according to the PVT fluctuation, the range in the fluctuation is not so large.

FIG. 7 is a diagram illustrating a precharge voltage control unit according to another exemplary embodiment of the present disclosure. Referring to FIG. 7, the precharge voltage control unit includes a first switch unit 50, a bleeder resistance unit 52 and a second switch unit 54 which connects node E to node F.

The first switch unit 50 includes an NMOS transistor N50 and a PMOS transistor P50 which are connected between node E and node F and are turned on in response to enable signals BLEEDER OFF and BLEEDER OFFB. Here, it is desirable to design the NMOS transistor N50 and the PMOS transistor P50 to have a large size.

The bleeder resistance unit 52 includes NMOS transistors N51 to N54 which are connected between node E to which the internal voltage Vp is applied and node F to which the precharge voltage VBLP is supplied and operate in response to the control signals BLEEDER_XL, BLEEDER_L, BLEEDER_M and BLEEDER_S, respectively, and resistance elements 10K, 20K, 40K and 80K which are in series connected with the NMOS transistors N51 to N54, respectively.

Operation of the precharge voltage supplying circuit of FIG. 7 will be described below in detail.

The bleeder resistance unit 52 operates in response to the enable signals BLEEDER OFF and BLEEDER OFFB. First, in a case that the enable signals BLEEDER OFF and BLEEDER OFFB are in high and low levels, respectively, the NMOS transistor N50 and the PMOS transistor P50 are turned on. Since the sizes of the NMOS transistor N50 and the PMOS transistor P50 are large, the voltage drop between node E and node F through the turn-on resistance of the NMOS transistor N50 and the PMOS transistor P50 is not so large. Thus, the second bit line precharge voltage VBLP, having a level which is almost the same as the internal voltage Vp, is output through node F. At this time, there is almost no voltage drop through the bleeder resistance unit 52 which includes the NMOS transistors N51 to N54 and the resistance elements 10K, 20K, 40K and 80K. Also, if the second switch unit 54 is turned on so that node E is connected to node F, operation of the bleeder resistance unit 52 is bypassed, and the second bit line precharge voltage VBLP, having a level which is almost the same as the internal voltage Vp, is output through node F.

Meanwhile, in a case that the enable signal BLEEDER OFF is in a low level, the NMOS transistor N50 and the PMOS transistor P50 are turned off. Thus, a voltage drop of the internal voltage Vp occurs through the bleeder resistance unit 52 so that the voltage-dropped signal is outputted as the precharge voltage VBLP through node F. At this time, since the bleeder resistance unit 52 includes the NMOS transistors N51 to N54 and the resistance elements 10K, 20K, 40K and 80K, the precharge voltage VBLP is adjustable in various levels according to a PVT fluctuation and the range in the fluctuation is not so large. At this time, the level of the precharge voltage VBLP is adjustable according to the control signals BLEEDER_XL, BLEEDER_L, BLEEDER_M and BLEEDER_S. For example, in a case that the control signals BLEEDER_L, BLEEDER_M and BLEEDER_S are in a low level and only the control signal BLEEDER_XL is in a high level, the part which outputs the precharge voltage VBLP through node F with the voltage drop of the internal voltage Vp becomes the NMOS transistor N54 which is turned on and the resistance element 80K. It is possible to generate the precharge voltage which has various voltage levels based on the selective activation of the control signals BLEEDER_XL, BLEEDER_L, BLEEDER_M and BLEEDER_S.

Although various examples and exemplary embodiments of a precharge voltage supplying circuit that can be used to generate a bit line precharge voltage for performing a bit line precharge operation are described in the present disclosure, it can also be widely used in various other devices which need generation of a voltage, a level of which is adjustable according to a PVT characteristic change, and a range in change of which is not so large.

Although examples and exemplary embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims. For example, elements and/or features of different examples and illustrative embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims.

The present disclosure claims priority to Korean applications numbers 10-2007-0026584 and 10-2007-0063927, filed on Mar. 19, 2007, and Jun. 27, 2007, respectively, the entire contents of each of which are incorporated herein by reference. 

1. A precharge voltage supplying circuit, comprising: a control signal generating unit for generating a first control signal in response to a power-up signal and a clock enable signal; and a precharge voltage control unit having a bleeder circuit and driving the bleeder circuit in response to the first control signal to control a precharge voltage.
 2. The circuit of claim 1, wherein the first control signal is activated when the power-up signal is applied to the control signal generating unit.
 3. The circuit of claim 1, wherein the control signal generating unit outputs the first control signal, which drives the bleeder circuit, in response to the clock enable signal after a predetermined time from an input of the power-up signal.
 4. The circuit of claim 1, wherein the control signal generating unit includes: a control unit driven in response to the power-up signal and a mode register set signal; an operation unit for performing a NAND operation on an output signal of the control unit and an inverted signal of the clock enable signal; and a signal generating unit for outputting the first control signal by buffering an output signal of the operation unit.
 5. The circuit of claim 4, wherein the control unit includes: a pull-up driving unit for pull-up driving a node in response to the power-up signal; a pull-down driving unit for pull-down driving said node in response to the mode register set signal; and a latch unit for latching a signal at said node.
 6. The circuit of claim 1, wherein the precharge voltage control unit includes: a first bleeder circuit for outputting the precharge voltage in response to the first control signal; and a second bleeder circuit for outputting the precharge voltage in response to a plurality of second control signals having different turn-on voltage levels.
 7. The circuit of claim 6, wherein the first bleeder circuit includes: a first driver for outputting the precharge voltage in response to the first control signal; and a second driver for outputting the precharge voltage in response to an inverted signal of the first control signal.
 8. The circuit of claim 6, wherein the second bleeder circuit includes a plurality of drivers for outputting the precharge voltage in response to the plurality of second control signals having the different turn-on voltage levels.
 9. A precharge voltage supplying circuit, comprising: a precharge voltage supplying unit for supplying a precharge voltage in response to a power-up signal and a clock enable signal; and an equalization unit for precharging a bit line and a bit bar line by using the precharge voltage.
 10. The circuit of claim 9, wherein the precharge voltage supplying unit includes: a control signal generating unit for generating a first control signal in response to the power-up signal and the clock enable signal; and a precharge voltage control unit for controlling the precharge voltage in response to the first control signal.
 11. The circuit of claim 10, wherein the control signal generating unit includes: a control unit driven in response to the power-up signal and a mode register set signal; an operation unit for performing a NAND operation on an output signal of the control unit and an inverted signal of the clock enable signal; and a signal generating unit for outputting the first control signal by buffering an output signal of the operation unit.
 12. The circuit of claim 10, wherein the precharge voltage control unit includes: a first bleeder circuit for outputting the precharge voltage to the equalization unit in response to the first control signal; and a second bleeder circuit for outputting the precharge voltage to the equalization unit in response to a plurality of second control signals having different turn-on voltage levels.
 13. The circuit of claim 12, wherein the first bleeder circuit includes: a first driver for outputting the precharge voltage to the equalization unit in response to the first control signal; and a second driver for outputting the precharge voltage to the equalization unit in response to an inverted signal of the first control signal.
 14. The circuit of claim 12, wherein the second bleeder circuit includes a plurality of drivers for outputting the precharge voltage to the equalization unit in response to the plurality of second control signals having the different turn-on voltage levels.
 15. A precharge voltage supplying circuit, comprising: a control signal generating unit for generating a first control signal which is activated at the time of a power-up; a precharge voltage control unit for controlling a precharge voltage in response to the first control signal; and an equalization unit for precharging a bit line and a bit bar line by using the precharge voltage.
 16. The circuit of claim 15, wherein the control signal generating unit includes: a control unit driven in response to a power-up signal and a mode register set signal; an operation unit for performing a NAND operation on an output signal of the control unit and an inverted signal of a clock enable signal; and a signal generating unit for outputting the first control signal by buffering an output signal of the operation unit.
 17. The circuit of claim 15, wherein the precharge voltage control unit includes: a first bleeder circuit for outputting the precharge voltage to the equalization unit in response to the first control signal; and a second bleeder circuit for outputting the precharge voltage to the equalization unit in response to a plurality of second control signals having different turn-on voltage levels.
 18. The circuit of claim 17, wherein the first bleeder circuit includes: a first driver for outputting the precharge voltage to the equalization unit in response to the first control signal; and a second driver for outputting the precharge voltage to the equalization unit in response to an inverted signal of the first control signal.
 19. The circuit of claim 17, wherein the second bleeder circuit includes a plurality of drivers for outputting the precharge voltage to the equalization unit in response to the plurality of second control signals having the different turn-on voltage levels.
 20. A precharge voltage supplying circuit, comprising: a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied; a resistance element connected in parallel to the transistor between the first node and the second node; a logic unit configured to receive a test mode signal and produce an enable signal; and a switching element for connecting the first and second nodes in response to the enable signal from the logic unit.
 21. The circuit of claim 20, wherein the precharge voltage is supplied to a pair of bit lines in response to a bit line equalizing control signal.
 22. The circuit of claim 20, wherein the precharge voltage is produced by a voltage drop across the resistance element or by a voltage drop across the transistor which is turned on in response to the control signal.
 23. A precharge voltage supplying circuit, comprising: a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied; a resistance element connected in series to the transistor between the first node and the second node; a logic unit configured to receive a test mode signal and produce an enable signal; and a switching element for connecting the first and second nodes in response to the enable signal from the logic unit.
 24. The circuit of claim 23, wherein the precharge voltage is supplied to a pair of bit lines in response to a bit line equalizing control signal.
 25. The circuit of claim 23, wherein the logic unit includes a NOR gate for a NOR operation of a ground voltage signal and the test mode signal. 